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CXD2932AGA-2
GPS Base Band LSI
Description The CXD2932AGA-2 is a dedicated LSI for the GPS (Global Positioning System) satellite-based position measurement system. This LSI contains a 32-bit RISC CPU, satellite tracking circuit, 2M-bit mask ROM, RAM, UART, interval timer, and others. This LSI, used together with the RF LSI, enables the configuration of a 2-chip system capable of measuring its position anywhere on the globe. Features * 16-channel GPS receiver capable of simultaneously receiving 16 satellites * Supports differential GPS -- Conforms to RTCM SC-104 Ver. 2.1 -- Supports DARC * All-in-view measurement * Timer supporting GPS time * 32-bit RISC CPU * 256K-byte program ROM * 40K-byte RAM * Power management function * 1PPS supported * 2-channel UART * 4-channel interval timer * 16-bit general-purpose I/O port * 12-bit successive approximation system A/D converter (4-channel analog switch) Structure Silicon gate CMOS IC 144 pin LFLGA (Plastic)
Absolute Maximum Ratings * Supply voltage VDD VSS - 0.5 to 4.6
* Input voltage VI VSS - 0.5 to VDD + 0.5 * Output voltage VO VSS - 0.5 to VDD + 0.5 * Operating temperature Topr -40 to +85 C * Storage temperature Tstg -50 to +150 C Recommended Operating Conditions 3.0 to 3.6 * Supply voltage VDD * Operating temperature Topr -40 to +85 Input/Output Pin Capacitance * Input capacitance CIN 9 (Max.) * Output capacitance COUT 11 (Max.) * I/O capacitance CI/O 11 (Max.)
V V V
V C
pF pF pF
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E03202A37
CXD2932AGA-2
Performance * 16-channel GPS receiver * 32-bit RISC CPU * Receiver frequency: 1575.42MHz (L1 band, CA code) * Reception sensitivity Tracking sensitivity: -145dBm or less (typ.) when using the antenna of 25dBi, NF = 2dB and the RF amplifier with the 25dB gain for the RF block Reference data using the Sony's reference board. This value is not guaranteed, depending on the conditions. * Time to First Fix (time until initial measurement after power-on) Cold Start (without both ephemeris and almanac): 27 to 58s Warm Start (without ephemeris with almanac): 23 to 45s Hot Start (with both ephemeris and almanac): 6 to 17s Reference data with elevation angle of 5 or more and no interception environment on June, 2002. Positioning time with 90% possibility. These values are not guaranteed, depending on the conditions. * Positioning accuracy 2DRMS: approx. 5m Reference data with elevation angle of 5 or more and no interception environment on June, 2002. This value is not guaranteed, depending on the conditions. * Measurement data update time: 1s * Communication format: Sony Binary NMEA-0183 Customized NMEA (9600bps) * All-in-view
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CXD2932AGA-2
Block Diagram
JTAG (ARM-CORE) JTAG TCXO/XTCXO (OSC) CLKI/CLKO (OSC) CLKOUT ARM-CORE (A7TDMI) ARM7TDMI ARBITER (ARBITER) XPWRS XRS DECODER (DECODER) TIC (TIC) XGBE XROMI ROMW CLKS[2:0] TEST[1:0]
XWE[3:0] XCS[3:0] XOE
TAP-CTL (DFTC6) CLKGEN (CLKGEN)
BIST (SRAM) SCAN 9 to 18MHz (ARM) 18MHz (TCXO) 6MHz (USB)
System (SYS_REG) Interrupt (INT_CNTL) SSD1: 17ch (SSD1) XINT[1:0] IFI/IFO(OSC) REFCK A/D Timer: 3ch (TMITU)
AHB
APB
SRAM: 40KB (DMEM_40KB) ROM: 256KB (IMEM_M)
32k-Timer (ITU32K) UART: 2ch (DUART) USB/DRV (USB) PORT (PORT) ADDR: 20 bit DATA: 32 bit RXD[1:0] TXD[1:0] USB-I/F
ADDR: 32 bit DATA: 32 bit APB-Bridge (APBIF) ADDR: 20 bit DATA: 32 bit
ED[31:0] EA[19:0]
BUS-I/F (SMI)
PORT[15:0]
AHB: AMBA High Performance Bus APB: AMBA Peripheral Bus TIC: Test Interface Controller
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CXD2932AGA-2
Pin Configuration (Top View)
70 XWE2 75 ROMW 78 VDD3 81 ED4 83 ED6 86 ED8 87 ED9 90 VDD4 91 ED12 94 ED15 95 ED16 98 ED18 100 ED20 103 ED22 106 ED25
67 XINT1 71 XWE3 74 XROMI 77 ED1 79 ED2 82 ED5 85 ED7 89 ED11 92 ED13 96 VSS5 99 ED19 102 VDD5 104 ED23 107 ED26 111 ED29
64 XRS 68 XWE0 72 VSS3 73 XOE 76 ED0 80 ED3 84 VSS4 88 ED10 93 ED14 97 ED17 101 ED21 105 ED24 108 VSS6 110 ED28 114 VDD6
62 GBE 66 VDD2 69 XWE1
59 CLKO 63 XPWRS 65
58 CLKI 60 VSS2 61
55 CLKS0 56
54 VDD1 53
51 VSS1 49
50 AVS3 46 AVS1 44 AVS2
47 AVD3 43 VRT 40 VIN2
45 AVD1 41 VIN3 37 AVD2
42 VRB 38 VIN0 36 VDD11 33 TDI 29 VSS11 25 TEST0 21 RXD1 16
39 VIN1 35 TMS 32 TCK 30
34 TDO 31 TRST 28 CCKO 26
CLKS1 XTCXO USBDP 57 52 48
XINT0 CLKOUT CLKS2
TCXO USBDM
REFCK TEST1 27 CCKI 24 IFO 20 TXD1 17 23 IFI 22 VDD10 19 RXD0 18
PORT14 PORT15 TXD0 12 13 15
PORT11 PORT12 VSS10 8 VDD9 4 10 14
PORT9 PORT13 7 11
PORT4 PORT7 PORT10 1 VSS9 109 ED27 113 ED31 117 EA2 112 ED30 115 EA0 119 EA4 116 EA1 118 EA3 122 EA6 120 VSS7 121 EA5 123 EA7 124 EA8 125 EA9 126 VDD7 129 EA12 128 EA11 127 EA10 133 EA15 132 VSS8 130 EA13 137 EA19 135 EA17 131 EA14 141 XCS2 138 VDD8 134 EA16 144 5 9
PORT5 PORT8 2 6
PORT1 PORT2 PORT6 140 XCS1 136 EA18 143 3
PORT0 PORT3 139 XCS0 142 XCS3
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CXD2932AGA-2
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Symbol VSS9 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 VDD9 PORT8 PORT9 PORT10 PORT11 PORT12 PORT13 VSS10 PORT14 PORT15 TXD0 RXD0 TXD1 RXD1 VDD10 IFI IFO TEST0 TEST1 CCKI CCKO VSS11 REFCK TRST TCK TDI TDO TMS VDD11 AVD2 I/O -- VSS Description
I/O/Z I/O port 2 (See the Application Circuit for setting.) I/O/Z I/O port 3 (See the Application Circuit for setting.) I/O/Z I/O port 4 (See the Application Circuit for setting.) I/O/Z I/O port 5 (See the Application Circuit for setting.) I/O/Z I/O port 6 (See the Application Circuit for setting.) I/O/Z I/O port 7 (See the Application Circuit for setting.) -- VDD I/O/Z I/O port 8 (See the Application Circuit for setting.) I/O/Z I/O port 9 (See the Application Circuit for setting.) I/O/Z I/O port 10 (See the Application Circuit for setting.) I/O/Z I/O port 11 (See the Application Circuit for setting.) I/O/Z I/O port 12 (See the Application Circuit for setting.) I/O/Z I/O port 13 (See the Application Circuit for setting.) -- VSS I/O/Z I/O port 14 I/O/Z I/O port 15 O/Z I O/Z I -- I O I I I O -- I I I I O/Z I -- -- UART transmission data (CH0) UART reception data (CH0) UART transmission data (CH1) UART reception data (CH1) VDD IF signal binary conversion circuit Test (Low level fixed) Test (Low level fixed) Timer oscillation circuit (32.768kHz 100ppm) VSS Test (Low level fixed) Test (Open) Test (Open) Test (Open) Test Test (Open) VDD A/D converter VDD -5-
CXD2932AGA-2
Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
Symbol VIN0 VIN1 VIN2 VIN3 VRB VRT AVS2 AVD1 AVS1 AVD3 USBDM USBDP AVS3 VSS1 TCXO XTCXO VDD1 CLKS0 CLKS1 CLKS2 CLKI CLKO VSS2 CLKOUT GBE XPWRS XRS XINT0 VDD2 XINT1 XWE0 XWE1 XWE2 XWE3 VSS3 XOE XROMI
I/O I I I I I I -- -- -- -- Analog input (CH0) Analog input (CH1) Analog input (CH2) Analog input (CH3) Reference input (Bottom) Reference input (Top) A/D converter VSS PLL VDD PLL VSS USB VDD
Description
I/O/Z USB data + (Not supported in this IC. Pull down with 15k) I/O/Z USB data - (Not supported in this IC. Pull down with 15k) -- -- I O -- I I I I O -- O/Z I I I I -- I O O O O -- O I USB VSS VSS TCXO crystal oscillator (18.414MHz 3ppm) VDD CPU clock selection (CLKS2, CLKS1, CLKS0) = (0, 0, 1): 18.414MHz (TCXO) (CLKS2, CLKS1, CLKS0) = (0, 1, 0): 27.671MHz (TCXO x 1.5) CPU clock oscillator VSS 1PPS output External bus enable (H-Active) Oscillator enable (H-Active) Reset (L-Active) External interruption 0 (L-Active) VDD External interruption 1 (L-Active) External expansion write signal 0 External expansion write signal 1 External expansion write signal 2 External expansion write signal 3 VSS External expansion read signal Program area selection (Low: Internal / High: External) -6-
CXD2932AGA-2
Pin No. 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
Symbol ROMW ED0 ED1 VDD3 ED2 ED3 ED4 ED5 ED6 VSS4 ED7 ED8 ED9 ED10 ED11 VDD4 ED12 ED13 ED14 ED15 ED16 VSS5 ED17 ED18 ED19 ED20 ED21 VDD5 ED22 ED23 ED24 ED25 ED26 VSS6 ED27 ED28 ED29
I/O I Test (Low level fixed)
Description
I/O/Z External expansion data 0 I/O/Z External expansion data 1 -- VDD I/O/Z External expansion data 2 I/O/Z External expansion data 3 I/O/Z External expansion data 4 I/O/Z External expansion data 5 I/O/Z External expansion data 6 -- VSS I/O/Z External expansion data 7 I/O/Z External expansion data 8 I/O/Z External expansion data 9 I/O/Z External expansion data 10 I/O/Z External expansion data 11 -- VDD I/O/Z External expansion data 12 I/O/Z External expansion data 13 I/O/Z External expansion data 14 I/O/Z External expansion data 15 I/O/Z External expansion data 16 -- VSS I/O/Z External expansion data 17 I/O/Z External expansion data 18 I/O/Z External expansion data 19 I/O/Z External expansion data 20 I/O/Z External expansion data 21 -- VDD I/O/Z External expansion data 22 I/O/Z External expansion data 23 I/O/Z External expansion data 24 I/O/Z External expansion data 25 I/O/Z External expansion data 26 -- VSS I/O/Z External expansion data 27 I/O/Z External expansion data 28 I/O/Z External expansion data 29 -7-
CXD2932AGA-2
Pin No. 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Symbol ED30 ED31 VDD6 EA0 EA1 EA2 EA3 EA4 VSS7 EA5 EA6 EA7 EA8 EA9 VDD7 EA10 EA11 EA12 EA13 EA14 VSS8 EA15 EA16 EA17 EA18 EA19 VDD8 XCS0 XCS1 XCS2 XCS3 PORT0 PORT1
I/O I/O/Z External expansion data 30 I/O/Z External expansion data 31 -- O/Z O/Z O/Z O/Z O/Z -- O/Z O/Z O/Z O/Z O/Z -- O/Z O/Z O/Z O/Z O/Z -- O/Z O/Z O/Z O/Z O/Z -- O O O O VDD External expansion address 0 External expansion address 1 External expansion address 2 External expansion address 3 External expansion address 4 VSS External expansion address 5 External expansion address 6 External expansion address 7 External expansion address 8 External expansion address 9 VDD External expansion address 10 External expansion address 11 External expansion address 12 External expansion address 13 External expansion address 14 VSS External expansion address 15 External expansion address 16 External expansion address 17 External expansion address 18 External expansion address 19 VDD External expansion chip select 0 External expansion chip select 1 External expansion chip select 2 External expansion chip select 3
Description
I/O/Z I/O port 0 (See the Application Circuit for setting.) I/O/Z I/O port 1 (See the Application Circuit for setting.)
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CXD2932AGA-2
Analog Characteristics (1) A/D Converter Characteristics Item Resolution Channel Differential linearity error (DLE) Integral linearity error (ILE) Sampling time Conversion time Reference power (Top) Reference power (Bottom) Analog input power Current consumption Applicable pins 1 Pin 43 2 Pin 42 3 Pins 38 to 41 VRT VRB VIN0-3 AVD = 3.0V AVD = 3.0V f = 18.414MHz -1.0 -1.0 5 15 VRB 0 VRB 5 AVD VRT VRT 4 +1.0 +1.0 Symbol Conditions Min. (AVD = 3.0 to 3.6V, Topr = -40 to +85C) Typ. Max. 12 Unit Bit Ch LSB LSB s s V V V mA 1 2 3 Applicable pins
(2) USB Characteristics Item Output impedance Output voltage (Low) Output voltage (High) Data rise delay time Data fall delay time Data delay time ratio Crossover voltage Current consumption (during operation) Current consumption (during suspension) Applicable pins Pins 48, 49 Symbol Zdrv VOL VOH Tr Tf Tr/Tf Vcrs Ica Icb Conditions -- RL = 1.5k to 3.6V RL = 1.5k to GND CL = 50pF CL = 350pF CL = 50pF CL = 350pF CL = 50pF or 350pF CL = 50pF or 350pF CL = 50pF and VCC = 3.6V VCC = 3.6V
(AVD = 3.0 to 3.6V, Topr = -40 to +85C) Min. 28 -- 2.8 75 -- 75 0.8 1.3 -- -- Typ. Max. 43 0.3 3.6 -- 300 -- 300 1.2 2.0 20 2 Unit V V ns ns ns ns -- V mA mA
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CXD2932AGA-2
DC Characteristics Item Input voltage (1) (COMS level) Input voltage (2) (5V interface) Input voltage (3) (Schmitt) Output voltage (1) Output voltage (2) Output voltage (3) Output voltage (4) (5V interface) High level Low level High level Low level High level Low level High level Low level High level Low level High level Low level High level Low level Symbol VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL VOH VOL Icur 3.0V, 27.671MHz 3.0V 3.0V IOH = -4.0mA IOL = 4.0mA IOH = -8.0mA IOL = 8.0mA IOH = -2.0mA IOL = 8.0mA IOH = -2.0mA IOL = 4.0mA 3.0V, 18.414MHz Conditions
(VDD = 3.0 to 3.6V, Topr = -40 to +85C) Min. 0.7VDD 0.2VDD 0.7VDD 0.7VDD 0.2VDD VDD - 0.4 0.4 VDD - 0.4 0.4 VDD - 0.8 0.4 VDD - 0.8 0.4 63 75 3 5 60 100 5.5 0.2VDD Typ. Max. Unit V V V V V V V V V V V V V V mA mA A A 7 6 5 4 3 2 Applicable pins 1
Current consumption When GPS (During normal measurement operation)
Current consumption (In backup mode) When internal timer used
When external Istb1 timer used Istb2
Applicable pins 1 Pins 25, 26, 31 to 33, 35, 55 to 57, 74 to 77, 79 to 83, 85 to 89, 91 to 95, 97 to 101, 103 to 107, 109 to 113 2 Pins 2 to 7, 9 to 14, 16, 17, 19, 21, 30, 62, 65, 67, 143, 144 (Use the resistor of 4.7k or less when the pull-down is performed.) 3 Pins 63, 64 4 Pins 34, 61 5 Pins115 to 119, 121 to 125, 133 to 137, 139 to 142, 68 to 71, 73, 76, 77, 79 to 83, 85 to 89, 91 to 95, 97 to 101, 103 to 107, 109 to 113 6 Pins 2 to 7, 9 to 14, 16, 17, 143, 144 7 Pins 18, 20
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CXD2932AGA-2
AC Characteristics (1) External Memory Read Timing (VDD = 3.0 to 3.6V, CL = 40pF, Topr = -40 to +85C, CPU clock = 18.4MIPS) Item Read cycle time (0WAIT)1 Read cycle time (1WAIT)1 Read cycle time (2WAIT)1 Read cycle time (3WAIT)1 Address delay time Read signal fall delay time Read signal rise delay time Read data setup time Read data hold time Symbol Trcy0 Trcy1 Trcy2 Trcy3 Tca Tcfo Tcro Tds Tdh 0 2 2 22 0 Min. Typ. 54 108 162 216 4 10 10 Max. Unit ns ns ns ns ns ns ns ns ns
1 0WAIT (normal), 1 to 3WAIT (settable according to the program)
Tsys (1 to 4)
Tsys
Trcy0 to 3 XCS Tca EA Tcfo XOE Tcro Tca
ED Tds Tsys: CPU clock cycle Tdh
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CXD2932AGA-2
(2) External Memory Write Timing (VDD = 3.0 to 3.6V, CL = 40pF, Topr = -40 to +85C, CPU clock = 18.4MIPS) Item Write cycle time (0WAIT)1 Write cycle time (1WAIT)1 Write cycle time (2WAIT)1 Write cycle time (3WAIT)1 Address delay time Write signal fall delay time Write signal rise delay time Write data setup time Write data hold time Symbol Twcy0 Twcy1 Twcy2 Twcy3 Tca Tcfo Tcro Tds Tdh 0 2 2 2 2 Min. Typ. 162 216 270 324 4 6 8 15 10 Max. Unit ns ns ns ns ns ns ns ns ns
1 0WAIT (normal), 1 to 3WAIT (settable according to the program)
Tsys
Tsys (1 to 4)
Tsys'
Twcy0 to 3 XCS Tca Tca
EA Tcfo XWE Tcro
ED Tds Tsys: CPU clock cycle Tdh
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CXD2932AGA-2
Backup Mode When the power supply of the GPS receiver system is off (XPWRS = low: the external pull-down is necessary) and the reset state (XRS = low) is established, the device goes into the low power consumption state (backup mode) where the all oscillators except for the timer stop. The whole internal memory status at this time is retained and the Hot Start/Warm Start can be achieved. In order to cancel this mode, set the XRS pin to high after XPWRS is set to high and then the oscillation stabilization time and the PLL lock-in time are waited. (Normal operation / reset : VDD = 3.0 to 3.6V, backup mode : VDD = 2.0 to 3.6V)
Normal
Backup
Reset
Normal
OSC output XPWRS XRS Oscillation stabilization time PLL lock-in time (max. 1.0ms) ED[31:0], EA[19:0] PORT[15:0] XCS[3:0], XWE[3:0], XOE, XTCXO TXD[1:0], CLKOUT Pull-down output Hi-Z output High output Low output
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CXD2932AGA-2
Initialization Setting The device initialization is started by setting the reset pin (XRS) to low level. The timing should satisfy the conditions noted below. (1) During power-on (VDD = 3.0 to 3.6V, Topr = -40 to +85C) XPWRS should rise simultaneously with the power supply. XRS should rise 100ms or more after the power supply and XPWRS have risen.
VDD Power supply XPWRS 100ms or more VDD/2 XRS
VSS
(2) Initialization during operation (VDD = 3.0 to 3.6V, Topr = -40 to +85C) The internal registers can be initialized during operation by setting the XRS signal to low level for 100s or more. Keep the XPWRS signal at high level at this time. (The internal memory value is held.)
VDD
Power supply XPWRS XRS 1s or more VDD/2
VSS
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CXD2932AGA-2
Application Notes The constants shown in the circuits below are the examples, and do not guarantee the circuit operation. (1) TCXO input (a) When inputting the binary-converted signal The TCXO input signal should be 18.414MHz 3ppm.
Input
52
Open 53
(b) When performing the self-oscillation with the TCXO and XTCXO pins The TCXO input signal should be 18.414MHz 3ppm. For inputting the signal which is not binary converted, the signal should go through the DC cut capacitor.
0.01F Input 1M 53 52
(2) CPU clock generation (a) CPU clock selector The CLKS2, CLKS1 and CLKS0 pins are used to select that the TCXO clock is used or that the selfoscillation is performed with the CLKI and CLKO pins. Set the CLKI pin to low when the TCXO clock is used. (CLKS[2:0] = 001: recommendation) CLKS[2:0] 001 010 101 110 CLKI, CLKO -- -- 18 to 27MHz 12 to 18MHz CPU frequency TCXO x 1.0 (18.414MHz) TCXO x 1.5 (27.671MHz) CLKI x 1.0 (18 to 27MHz) CLKI x 1.5 (18 to 27MHz)
(b) When performing the self-oscillation with the CLKI and CLKO pins The crystal oscillator frequency should be within the values shown above.
22pF 58 12 to 27MHz 22pF 1M 59
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CXD2932AGA-2
(3) Timer clock setting When using the real-time clock (RTC) circuit in the device, connect the crystal oscillator of 32.768kHz 100ppm to the CCKI and CCKO pins. When using the external RTC circuit, set the CCKI pin to the low level. See the Port setting for the RTC internal/external selection.
22pF 27 32.768kHz 100ppm 28 22pF
(4) IF signal input This device's IF signal supports only 1.023MHz. When the signal which is not binary-converted is input, the signal should go through the DC cut capacitor.
0.01F Input 1M 24 23
(5) Serial input/output communication system See the corresponding data sheet for communication because the communication specification differs according to the communication format. See the Port setting for the communication format selection. The transmission data (TXD0 and TXD1) amplitude is 0.4V or less for the low level and VDD - 0.4V or more for the high level. When the LSI and others connected to this operate at 5V and the CMOS level input is used, convert 3V to 5V for input.
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CXD2932AGA-2
(6) Port setting When the power turns on or initialization setting is performed by the reset input, the system starts operation according to the selected port setting. Perform initialization after the setting is changed because the setting can not be changed during operation. Port 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I/O For reset I I I I I I I I I I I I I I I I For operation I I I I I I O O O I O I O I/O O O Description Test pin (Low = Normal mode) Communication format selection PORT[2:1] = (00: Sony Binary, 01: NMEA4800, 10: NMEA9600, 11: Unused) RTC selection (High = Internal / Low = External) Test pin (High = Normal mode) Test pin (Low = Normal mode) Unused Unused Unused Antenna sense (Low = Disable / High = Enable) Antenna shutdown (High = Cut) Test pin (Low = Normal mode) Unused RTC SIO (Leave open when the internal RTC is selected.) RTC SCL (Leave open when the internal RTC is selected.) RTC CE (Leave open when the internal RTC is selected.)
(7) A/D setting The antenna sense function can be realized by connecting the antenna power supply of the GPS receiver to the A/D channel pins shown below. See the Application Circuit for the resistance value and others. See the Port setting for the antenna sense function disable/enable selection. VIN 0 1 2 3 I/O For reset I I I I For operation I I I I Description Antenna power supply (before current value detection resistor) Antenna power supply (after current value detection resistor) Test pin (Low level fixed) Test pin (Low level fixed)
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Application Circuit
VSS VDD 0.1 0.1 0.1 VSS VDD
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
ED17
ED12
ED7
ED23
ED22
ED18
ED13
ED8
ED3
ED2
XROMI
ED9
ED4
ROMW
ED24
ED19
ED14
ED25
ED20
ED15
ED10
ED5
ED26
ED11
ED21
ED16
VSS6
VDD5
VSS5
VDD4
VSS4
ED6
VDD3
ED1
ED0
XOE
TC55V16256FTI
VSS3 72 XWE3 71 XWE2 70 XWE1 69 XWE0 68 XINT1 67 VDD2 66 XINT0 65 XRS 64 0.1 EA5 EA4 EA3 EA2 EA1 XCS0 ED16 ED17 ED18 0 1 A4 2 A3 3 A2 4 A1 5 A0 6 CE 7 I/O1 8 I/O2 9 I/O3 A5 44 A6 43 A7 42 OE 41 UB 40 LB 39 I/O16 38 I/O15 37 I/O14 36 I/O13 35 GND 34 VDD 33 I/O12 32 I/O11 31 I/O10 30 I/O9 29 NU 28 A8 27 A9 26 A10 25 A11 24 A17 23 EA9 EA10 EA11 EA12 EA13 ED31 ED30 ED29 ED28 0.1 EA6 EA7 EA8 XOE EA5 EA4 EA3 EA2 EA1 XCS0 ED0 ED1 ED2 1 2 3 4 5 6 7 8 9
TC55V16256FTI
A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 A5 44 A6 43 A7 42 OE 41 UB 40 LB 39 I/O16 38 I/O15 37 I/O14 36 I/O13 35 GND 34 VDD 33 I/O12 32 I/O11 31 I/O10 30 I/O9 29 NU 28 A8 27 A9 26 A10 25 A11 24 A17 23 EA9 EA10 EA11 EA12 EA13 ED15 ED14 ED13 ED12 0.1 ED11 ED10 ED9 ED8 EA6 EA7 EA8 XOE
109 ED27 110 ED28 111 ED29 112 ED30 113 ED31 114 VDD6 0.1 115 EA0 116 EA1 117 EA2 118 EA3 119 EA4 120 VSS7 121 EA5 122 EA6 123 EA7 124 EA8 125 EA9 126 VDD7 0.1 127 EA10 128 EA11 129 EA12 130 EA13
XPWRS 63 GBE 62 CLKOUT 61 VSS2 60 CLKO 59 CLKI 58 CLKS2 57 CLKS1 56 CLKS0 55 VDD1 54 XTCXO 53 TCXO 52 VSS1 51 AVS3 50 USBDP 49 USBDM 48 AVD3 47 AVS1 46 AVD1 45 AVS2 44 VRT 43 VRB 42 VIN3 41 VIN2 40 VIN1 39 VIN0 38 AVD2 37 47H 15k 15k 0.1 0.1 0.01 1M 0.1
ED19 10 I/O4 0.1 11 VDD 12 GND ED20 ED21 ED22 ED23 XWE1 EA16 EA15 EA14 EA13 EA17 13 I/O5 14 I/O6 15 I/O7 16 I/O8 17 WE 18 A15 19 A14 20 A13 21 A12 22 A16
ED3 10 I/O4 0.1 11 VDD 12 GND ED4 ED5 ED6 ED7 XWE1 EA16 EA15 EA14 EA13 EA17 13 I/O5 14 I/O6 15 I/O7 16 I/O8 17 WE 18 A15 19 A14 20 A13 21 A12 22 A16
ED27 ED26 ED25 ED24
CXD2932AGA-2
PORT14
PORT10
PORT11
PORT12
PORT13
PORT15
PORT3
PORT4
PORT5
PORT6
PORT7
PORT9
REFCK
PORT2
PORT8
TEST0
TEST1
VDD10
VSS10
RXD0
RXD1
TXD0
TXD1
VDD9
VDD11
CCKO
VSS11
TRST
VSS9
CCKI
TCK
TDO
TMS
IFO
4.7k
TDI
IFI
SCL
SIO
VSS
CE
OSCO
OSCI
INT
VDD
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0.1 VDD VSS
131 EA14 132 VSS8 133 EA15 134 EA16 135 EA17 136 EA18 137 EA19 138 VDD8 139 XCS0 140 XCS1 141 XCS2 142 XCS3 143 PORT0 144 PORT1
In external program mode (XROMI = H, GBE = H)
PORT10 15
47k
RN3112Q291A
3 GND 4 CD 0.1 VDD 2 OUT 1 47k
When using antenna sense function (PORT9 = H)
MAX6364LUT26
47H 0.1 1 RESET 2 GND 3 RESETIN BATT 6 OUT 5 VCC 4
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
4.7k
4.7k 1M 4.7k 0.1 0.1 PORT10 4 3 2 1 0.01 22p 22p
32.768k
VDD 0.1 VSS 0.1
3.0V ANT PWR 10H 47k 100 RESET 1PPS TCXO (18.414MHz) IF (1.023MHz) RXD1 RXD0 TXD0 VDD (3.3V) GND
When using on internal timer (PORT3 = H)
CXD2932AGA-2
5 32.768k 22p
6
7
8
22p
RS5C313 0.1 When using on external timer (PORT3 = L)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXD2932AGA-2
Package Outline
Unit: mm
144PIN LFLGA
0.2 SA 13.0
1.4MAX 0.01
PIN 1 INDEX
13.0
x4 0.15 S 3 - 0.50 0.55 R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 101 112131415 0.5 0.55 0.8 0.9 A 144 - 0.40 0.05 0.08 M S A B
0.2
0.20 S
SB
DETAIL X
0.55
B
0.55 0.5
0.9
0.8
PACKAGE STRUCTURE
PACKAGE MATERIAL ORGANIC SUBSTRATE NICKEL & GOLD PLATING COPPER 0.5g
SONY CODE EIAJ CODE JEDEC CODE
LFLGA-144P-01 P-LFLGA144-13x13-0.8
TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS
0.10 S
Sony Corporation
- 19 -
X

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